1. Field of the Invention
The invention relates in general to display devices and in particular to scrambling and encrypting devices and methods to prevent a signal "in the clear" at the display device.
2. Description of Related Art
To avoid pirating of video, video is scrambled or encrypted by the provider to protect against unauthorized viewing. The term "scrambling" typically means the altering of an analog signal such that it cannot be displayed in a conventional sense without the proper descrambling operation. Examples of scrambling techniques include, but are not limited to, sync suppression, active line rotation, and line shuffling. The term "encryption" typically is used to describe the operation of altering a digital sequence usually by multiplying it by a pseudo-random sequence. In order to recover the original signal, a "key" is required. An example of this technique is the Data Encryption Standard (DES).
An example of a typical MPEG display system without encryption is shown in FIG. 1. An example of a typical MPEG display system with encryption is shown in FIG. 2, where it should be noted that an encrypted sequence "BLCFADGIHEKJ" is created.
A video signal is often scrambled or encrypted so that without proper authorization, it is in an unusable form. However, if the consumer premises are granted authorization, then typically at interfaces which are accessible to the consumer, such as at the output of a cable converter box or the "video output" jacks of a receiver, the video signal is descrambled or decrypted and hence is "in the clear" (See FIG. 3).
There are many types of display devices available today. There is the generally well known cathode ray tube display devices (CRT), and discrete display devices such as digital light modulators or deformable mirror spatial light modulator (DMD), liquid crystal displays (LCD), and plasma displays. Each of these displays have the problems associated with an unauthorized user simply recording the video "in the clear" from the output of the cable converter box or the "video output" jacks of a television receiver. For ease of description however, reference will be had to the operation of a DMD.
A digital light modulating element is one which is capable of modulating incident light to two different luminance levels. In the simplest case, either a bright or a dark light level is produced. Typically the element is either light reflective or light transmissive. An advantage of this type of element is that it enables a display apparatus to be constructed which can be operated totally by the application of digital signals. This facilitates integration of the display and of associated digital drive circuitry on a chip.
A particular type of the spatial light modulator is the deformable-mirror device (DMD) which is described by Larry J. Hornbeck in "Deformable-Mirror Spatial Light Modulators", SPIE Vol. 1150, pages 86-102 (1990), (hereby incorporated by reference). The DMD incorporates, on an integrated circuit chip, a matrix array of individually-addressable, electrostatically-deflectable mirrors. Each mirror produces one light-modulated pixel of an image (e.g. figures, symbols or text) to be presented to a viewer.
U.S. Pat. No. 5,079,544, which is hereby incorporated by reference, describes in detail various display devices which utilize DMDs. Two of the drawing figures from that patent are included herein, in slightly modified form as FIGS. 4 and 5, to facilitate a general explanation of the operation of an exemplary DMD.
FIG. 4A is a diagram of a DMD integrated circuit chip including a timing circuit 14, an array 16 of deformable mirror cells, a register 18 (e.g. a shift register), and first and second decoders 22 and 24, respectively. The deformable mirror cells may be disposed in a matrix arrangement or in some other convenient arrangement. A typical arrangement is a row-and-column matrix where each cell is disposed at a crossing of a respective row and column conductor or line. This type of arrangement is presumed for purposes of describing and explaining the operation of the array 16. A memory cell, including a plurality of sub-cells for storing respective bits of a multi-bit display code, is associated with each mirror cell. The multi-bit display code enables different luminance levels to be achieved by varying the amount of time that the mirrors are ON or OFF. For a more detailed explanation of achieving the different luminance levels reference is made to U.S. Pat. No. 5,079,544 and U.S. Ser. No. 08/495,290.
The register 18 has a number of taps 20 for electrical connection to a bus (not shown) to enable data to be loaded into the register for transfer to respective memory cells in the array. The bus may provide data from a variety of different sources, such as an A/D converter driven by a video source (e.g. a television), a computer or a graphics system. The register 18 also has a number of outputs which are connected to respective column lines C.sub.1, C.sub.2 . . . C.sub.N of the array 16. Similarly, the decoder 22 has a number of outputs which are connected to respective row lines R.sub.1, R.sub.2 . . . R.sub.M of the array. Although not shown in FIG. 4A, the timing circuit 14 is electrically connected to the register 18 and to the decoders 22 and 24. The decoders themselves each include means, such as shift registers, for sequentially selecting the memory sub-cells in response to timing pulses from the timing circuit 14. In DMD devices the data can be loaded into the register sequentially to be read out sequentially. Thus if the signal is encrypted the decrypting must occur before the data is loaded into the register. This provides a signal "in the clear."
In response to timing signals produced by the timing circuit 14:
register 18 and decoder 22 sequentially select row and column lines to direct data from the register to the memory cells associated with selected mirror cells; PA1 decoder 22 also sequentially selects the memory sub-cells into which data from the register 18 is to be written; and PA1 decoder 24 sequentially reads the data from the memory sub-cells to activate the associated mirror cells.
FIG. 5 shows schematically an arbitrary three-bit memory cell of the DMD array 16, electrically connected to row line R.sub.m and column line C.sub.n. This figure also shows integrated circuitry associated with this memory cell, the mirror cell DM.sub.mn located at the crossing of row line R.sub.m and column line C.sub.n, with which the memory cell is associated, and connections to the register 18 and to the decoders 22 and 24.
This and each other memory cell in the array is formed by three single-bit inverting memory sub-cells 54,55,56 for storing respective bits of a three-bit binary display code. The data to be written into this memory cell is provided over column line C.sub.n from a respective output of register 18 to three electrically connected data lines 50,51,52 which, in turn, are selectively connected to inputs of the sub-cells through WRITE switching transistors 96,97,98, respectively. Selection of these transistors is controlled via row line R.sub.m which is formed by a group of three row conductors that are electrically connected to gates of the transistors 96,97,98 via gating lines 92,91,90 respectively. Note that column line C.sub.n is electrically connected to the data lines 50,51,52 of every memory cell in column n. Similarly, row line R.sub.m is electrically connected to the gating lines 92,91,90 of every memory cell in row m.
Reading of the stored data from the memory sub-cells is controlled by the decoder 24 having three outputs which are electrically connected via gating lines 84,85,86 to respective gates of three READ switching transistors 68,69,70. Outputs of the memory sub-cells are selectively connected via these transistors to an input 72 of a single-bit inverting memory cell 74. Note that gating lines 84,85,86 are electrically connected to corresponding READ switching transistors for every memory cell in the array.
The single-bit inverting memory cell 74 has an output electrically connected to the associated mirror cell DM.sub.mn. Specifically, the output of memory cell 74 is directly electrically connected to a control electrode 128 and is electrically connected through an inverter 129 to a control electrode 130. As is explained in detail in the SPIE article by Hornbeck and in U.S. Pat. No. 5,079,544, which have been incorporated by reference, when memory cell 74 produces a voltage representative of a logical ONE, this voltage effects deflection of reflective mirror element 116 to an ON position represented by the dashed line 118. Conversely, when memory cell 74 produces a voltage representative of a logical ZERO, this voltage effects deflection of reflective mirror element 116 to an OFF position represented by the dashed line 134. In the ON position, the mirror element 116 reflects light (from a source not shown in FIG. 5) and directs it toward a pixel at row m and column n on a display screen, which corresponds with the pixel represented by the memory cell. Conversely, in the OFF position, mirror element 116 directs the light away from the display screen. U.S. Ser. No. 08/495,290 (incorporated by reference) illustrates an example of how different luminance levels are achieved for each pixel while using the simple ON and OFF approach described above.
The pixel data are loaded into register and the addressable memory elements sequentially across each line, sequentially line-by-line, but all pixel elements for the entire display are modulated at the same time. This sequential loading, however, provides a signal "in the clear" which is easily pirated. There are similar signals "in the clear" for LCD devices, CRTs and plasma display devices.